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rev.1.00, apr.25.2 003, page 1 of 38 HD151TS207SS mother board clock generator for intel p4+ chipset (springdale) rej03d0006-0100z preliminary rev.1.00 apr.25.2003 description the HD151TS207SS is intel ck409t type high-performan ce, low-skew, low-jitter, pc motherboard clock generator. it is specifically designed for intel pentium ? 4+ chipset. features ? 3 differential pairs of current mode control cpu clocks ? 1 differential pair of serial reference clock (src), selectable 100 mhz/200 mhz ? 6 copies pci clocks and 3 copies pcif clocks @3.3v, 33.3 mhz ? 1 copy pci clock @3.3 v, selectable 33.3 mhz/25 mhz ? 1 copy usb clock @3.3 v, selectable 48 mhz/24 mhz ? 1 copy dot clock @3.3 v, 48 mhz ? 4 copies of 3v66 clocks @3.3 v, 66.6 mhz ? 1 copy of 3v66/vch clock @3.3 v, selectable 66.6 mhz/48 mhz ? 2 copies of ref clocks @3.3 v, 14.318 mhz ? power save and clock stop function ? i 2 c tm serial port programming ? programmable clock control (spread spectrum percentage, clock output skew, slew rate) ? watchdog timer and reset output ? 56pin ssop (300 mils) note: i 2 c is a trademark of philips corporation. pentium is registered trademark of intel corporation
HD151TS207SS rev.1.00, apr.25.2 003, page 2 of 38 key specifications ? supply voltages: vdd = 3.3 v5% ? cpu clock cycle to cycle jitter = |125ps| (ssc disabled) ? cpu clock group skew = 100ps ? 3v66 clock group skew = 250psmax ? pci clock group skew = 500psmax
HD151TS207SS rev.1.00, apr.25.2 003, page 3 of 38 pin arrangement 1 2 3 4 5 6 7 8 9 10 ref0 ref1 vdd_ref xtal_in xtal_out vss_ref fs2/pcif_0 fs4/pcif_1 vdd_pci vss_pci pci_1 mode/pci_0 pci_2 pci_3 vdd_pci vss_pci sel100_200/pci_4 sel33_25/pci_5 pci_6 pwrdwn#/safe_f# 3v66_0/reset# 3v66_1 vdd_3v66 pcif_2 11 12 13 14 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 vss_48 vdd_48 vtt_pwrgd# src# src cpu_1 cpu_0# cpu_0 vss_cpu cpu_2 vdd_cpu pci_stop# vss_src test_clk# fs_a iref vss_a fs_b vdd_a vdd_src vss_3v66 3v66_2 3v66_3 sclk 25 26 27 28 29 30 31 32 sel66_48/3v66_4/vch sdata sel48_24/usb_48 fs3/dot_48 vdd_cpu cpu_1# cpu_2# vss_iref (top view) pci_stop#, pwrdwn# = 150 k internal pull-up
HD151TS207SS rev.1.00, apr.25.2 003, page 4 of 38 pin descriptions pin name no. type description vss_a 54 ground for pll vss_cpu 45 ground for outputs vss_iref 53 ground for current reference vss_src 39 vss_3v66 25 vss_pci 11, 17 vss_ref 6 vss_48 33 ground ground for outputs vdd_a 55 3.3 v power supply for pll vdd_cpu 42, 48 vdd_src 36 vdd_3v66 24 vdd_pci 10, 16 vdd_ref 3 vdd_48 34 power 3.3 v power supply for outputs ref0 1 ref1 2 output 3.3 v 14.318 mhz reference clock. xtal_in 4 input 14.318 mhz xtal input. xtal_out 5 output 14.318 mhz xtal output. don?t connect when an external clock is applied at xtal_in. fs2/pcif_[0:1] 7,8 input/ output frequency select latch input pin. /free running pci clock 3.3 v output. pcif_2 9 output free running pci clock 3.3 v output. **mode/pci_0 12 input/ output function select latch input pin for pin 22, 1 = reset#, 0 = clock output. /pci clock 3.3 v output. pci_[1:3] 13,14, 15 output pci clock 3.3 v outputs. **sel100_200/ pci_4 18 input/ output latched select input for src output. 1 = 200 mhz, 0 = 100 mhz /pci clock 3.3 v output. **sel33_25/pci_5 19 input/ output latched select inpu t for pci5 output. 1 = 25 mhz, 0 = 33 mhz /pci clock 3.3 v output. pci_6 20 output pci clock 3.3 v outputs. note: (*): those pins are 150 k ? internal pulled-up. (**): those pins are 150 k ? internal pulled-down.
HD151TS207SS rev.1.00, apr.25.2 003, page 5 of 38 pin descriptions (cont.) pin name no. type description pwrdwn#/ safe_f# 21 input pull?up* pwrdwn# / safe_f# selectable input. default is pwrdwn# input. byte15[5] = ?1? : safe_f# input. pwrdwn# is all clocks stop pin. asynchronous active ?low? input. when asserted low, all output clocks are disabled. safe_f# is active ?low? input. when safe_f# is ?low? ,frequency mode is changed to the predefined frequency mode. 3v66_0/reset# 22 output 3v66 / watc hdog reset# selectable output. default is 3v66 output. this signal is active low and selected by mode latch input. 3v66_[1:3] 23,26, 27 output 3v66 clock 3.3v outputs. sclk 28 input pull-up* clock input for i 2 c logic. **sel66_48/ 3v66_4/vch 29 input/ output latched select input for 3v66/vch output 1 = 48 mhz, 0 = 66.66 mhz. /3v66 or vch clock output. sdata 30 in/output pull-up* data input for i 2 c logic. **sel48_24/ usb_48 31 input/ output latched select input for 48_24 mhz output 1 = 24 mhz, 0 = 48 mhz / 24_48 mhz clock 3.3 v output. fs3/dot_48 32 input/ output frequency select latch input pin. /dot_48 clock 3.3 v output. vtt_pwrgd# 35 input pull-up* qualifying input that latches fs_a and fs_b. when asserted low, fs_a and fs_b are latched. src# 37 output ?complementary? clock of differential serial reference clock. src 38 output ?true? clock of differential serial reference clock. cpu_[0:2]# 40,43, 46 output ?complementary? clock of differential cpu clock. cpu_[0:2] 41,44, 47 output ?true? clock of differential cpu clock. pci_stop# 49 input pull?up* pci clocks stop pin. active ?low? input. when asserted low, pci[6:0] and src clocks are synchronously disabled in low state. usually this pin does not give to effect pcif[2 :0] clock outputs. test_clk# 50 input pull-up* test clock mode pin. active ?low? input. fs_[a:b] 51,52 input cpu clocks frequency select latch input. iref 52 input a precision resistor is attached to this pin which is connected to internal cu rrent reference. a resistor is connected between this pin and gndiref. note: (*): those pins are 150 k ? internal pulled-up. (**): those pins are 150 k ? internal pulled-down
HD151TS207SS rev.1.00, apr.25.2 003, page 6 of 38 block diagram 3v66[3:1] 1/m2 ssc2 1/n2 1/m1 ssc1 1/n1 1/m0 1/n0 osc ck2 ck1 ck0 xtal 14.318 mhz ref[1:0] (14.318mhz) cpu[2:0] cpu[2:0]# * : latched input pin. 3.3 v vdd_48 3.3 v vdd_a vss_48 vss_a 6 3.3v vdd 6 vss vss_iref iref pci[6:0] src# src *sel48_24 *fs_4/3/2a/b *sel33_25 *mode test_clk# *sel66_48 *sel100_200 vtt_pwrgd# pwrdwn#/safe_f# pci_stop# sclk sdata input clock select pll2 for cpu usb pll pll1 for src 3v66 pci pcif[2:0] 3v66_0/reset# 3v66_4/vch usb_48 dot_48 control logic vco0 vco1 vco2 clock divider clock select delay control stop control
HD151TS207SS rev.1.00, apr.25.2 003, page 7 of 38 i 2 c controlled register bit map byte0 control register bit description contents type default note 7 reserved r 0 6 reserved r 0 5 reserved r 0 4 reserved r 0 3 pci_stop reflects the current value of the external pci_stop# pin 0 = pci_stop# pin is low 1 = pci_stop# pin is high rx 2 reserved r x 1 fs_b reflects the value of the fs_b pin sampled on power up 0 = fs_b low at power up 1 = fs_b high at power up rx 0 fs_a reflects the value of the fs_a pin sampled on power up 0 = fs_a low at power up 1 = fs_a high at power up rx see table 1 table1 clock frequency function table byte6 bit5 fs_a fs_b cpu [mhz] src [mhz] 3v66 [mhz] pcif pci [mhz] ref0 ref1 [mhz] usb dot [mhz] note 0 0 0 100 100/200 66 33 14.318 48 0 0 1 200 100/200 66 33 14.318 48 0 1 0 133 100/200 66 33 14.318 48 0 1 1 166 100/200 66 33 14.318 48 1 0 0 200 100/200 66 33 14.318 48 1 0 1 400 100/200 66 33 14.318 48 1 1 0 266 100/200 66 33 14.318 48 1 1 1 333 100/200 66 33 14.318 48 table2 test clock select table test_clk# cpu [mhz] src [mhz] 3v66 [mhz] pcif pci [mhz] ref0 ref1 [mhz] usb dot [mhz] note 1 ref/2 ref/2 ref/4 ref/8 ref ref/2 0 hi?z hi?z hi?z hi?z hi?z hi?z see note1, table3 note: 1. ref is a clock over driven on the xin during test mode.
HD151TS207SS rev.1.00, apr.25.2 003, page 8 of 38 i 2 c controlled register bit map (cont.) table3 fs_a and fs_b pin input level logic level min voltage max voltage 0 (low) ? 0.35v 1 (high) 0.70v ? bit description contents type default note 7 allow control of scr with assertion of pci_stop# 0 = free running 1 = stopped with pci_stop# rw 0 see table5 6 src output enable 0 = disabled (tristate) 1 = enabled rw 1 5 reserved rw 1 4 reserved rw 1 3 reserved rw 1 2 cpu2 output enable 0 = disabled (tristate) 1 = enabled rw 1 1 cpu1 output enable 0 = disabled (tristate) 1 = enabled rw 1 0 cpu0 output enable 0 = disabled (tristate) 1 = enabled rw 1 byte2 control register bit description contents type default note 7 src_pwrdwn drive mode 0 = driven in power down, 1 = tristate rw 0 6 src_stop drive mode 0 = driven when stopped, 1 = tristate rw 0 see table5 5 cpu2_pwrdwn drive mode 0 = driven in power down, 1 = tristate rw 0 4 cpu1_pwrdwn drive mode 0 = driven in power down, 1 = tristate rw 0 3 cpu0_pwrdwn drive mode 0 = driven in power down, 1 = tristate rw 0 2 reserved rw 0 1 reserved rw 0 0 reserved rw 0 see table4
HD151TS207SS rev.1.00, apr.25.2 003, page 9 of 38 i 2 c controlled register bit map (cont.) table4 cpu clock power management truth table signal pin pwrdwn# pwrdwn# tristate bit byte2[5:3] non-stop outputs byte1[5:3] = 1 note cpu[2:0] 1 x running cpu[2:0] 0 0 driven @ iref x2 see note1 cpu[2:0] 0 1 tristate note: 1. iref = vdd/(3rr) = 3.3/(3x475) = 2.32 ma, iref x2 = 4.6 ma (voh @z: 0.23 v @50 ? ) table5 src clock power management truth table signal pin pwrdwn# pin pci_stop# pci_stop# tristate bit byte2[6] pwrdwn# tristate bit byte2[7] non-stop outputs byte1[7] = 1 stoppable outputs byte1[7] = 0 note src 1 1 x x running running src100xrunningdriven @ iref x6 see note1 src101xrunningtristate src 0 x x 0 driven @ iref x2 driven @ iref x2 see note1 src 0 x x 1 tristate tristate note: 1. iref = vdd/(3rr) = 3.3/(3x475) = 2.32 ma iref x6 = 13.9 ma (voh @z: 0.7 v @50 ? ) iref x2 = 4.6 ma (voh @z: 0.23 v @50 ? ) byte3 control register bit description contents type default note 7 pci_stop control 0 = enabled, all stoppable pci and src clocks are stopped. 1 = disabled rw 1 6 pci_6 output enable 0 = disabled, 1 = enabled rw 1 5 pci_5 output enable 0 = disabled, 1 = enabled rw 1 4 pci_4 output enable 0 = disabled, 1 = enabled rw 1 3 pci_3 output enable 0 = disabled, 1 = enabled rw 1 2 pci_2 output enable 0 = disabled, 1 = enabled rw 1 1 pci_1 output enable 0 = disabled, 1 = enabled rw 1 0 pci_0 output enable 0 = disabled, 1 = enabled rw 1
HD151TS207SS rev.1.00, apr.25.2 003, page 10 of 38 i 2 c controlled register bit map (cont.) byte4 control register bit description contents type default note 7 usb_48 2x output drive 0 = 2x drive strength, 1 = normal rw 0 6 usb_48mhz output enable 0 = disabled, 1 = enabled rw 1 5 allow control of pcif_2 with assertion of pci_stop# 0 = free running 1 = stopped with pci_stop# rw 0 4 allow control of pcif_1 with assertion of pci_stop# 0 = free running 1 = stopped with pci_stop# rw 0 3 allow control of pcif_0 with assertion of pci_stop# 0 = free running 1 = stopped with pci_stop# rw 0 2 pcif_2 output enable 0 = disabled, 1 = enabled rw 1 1 pcif_1 output enable 0 = disabled, 1 = enabled rw 1 0 pcif_0 output enable 0 = disabled, 1 = enabled rw 1 byte5 control register bit description contents type default note 7 dot_48mhz output enable 0 = disabled, 1 = enabled rw 1 6 reserved rw 1 5 vch select 66mhz / 48mhz 0 = 3v66 mode 1 = vch (48 mhz) mode rw 0 4 3v66_4/vch output enab le 0 = disabled (tristate), 1 = enabled rw 1 3 3v66_3 output enable 0 = disabled, 1 = enabled rw 1 2 3v66_2 output enable 0 = disabled, 1 = enabled rw 1 1 3v66_1 output enable 0 = disabled, 1 = enabled rw 1 0 3v66_0 output enable 0 = disabled, 1 = enabled rw 1 byte6 control register bit description contents type default note 7 test clock mode 0 = disabled, 1 = enabled rw 0 6 reserved rw 0 5 fs_a & fs_b operation 0 = normal, 1 = test mode rw 0 4 src frequency select 0 = 100mhz, 1 = 200 mhz rw 0 3 reserved rw 0 2 spread spectrum mode 0 = spread off 1 = spread on rw 0 see b9[7:6] 1 ref1 output enable 0 = disabled, 1 = enabled rw 1 0 ref0 output enable 0 = disabled, 1 = enabled rw 1
HD151TS207SS rev.1.00, apr.25.2 003, page 11 of 38 i 2 c controlled register bit map (cont.) byte7 vendor identification register bit description contents type default note 7 revision code bit3 vendor specific r 0 6 revision code bit2 vendor specific r 0 5 revision code bit1 vendor specific r 0 4 revision code bit0 vendor specific r 1 3 vendor id bit3 vendor specific r 1 2 vendor id bit2 vendor specific r 1 1 vendor id bit1 vendor specific r 1 0 vendor id bit0 vendor specific r 1 byte8 read back byte count register bit description contents type default note 7 read back byte count bit7 rw 0 6 read back byte count bit6 rw 0 5 read back byte count bit5 rw 0 4 read back byte count bit4 rw 1 3 read back byte count bit3 rw 1 2 read back byte count bit2 rw 1 1 read back byte count bit1 rw 1 0 read back byte count bit0 writing to this register will configure byte count and how many bytes will be read back. default is 1ehex = 30 bytes. rw 0
HD151TS207SS rev.1.00, apr.25.2 003, page 12 of 38 i 2 c controlled register bit map (cont.) byte9 control register bit description contents type default note 7 ssc2 enable bit b6[2] = 0 or b9[7] = 1 : ssc2 =off b6[2] = 1 & b9[7] = 0 : ssc2 = on rw 0 6 ssc1 enable bit b6[2] = 0 or b9[6] = 1 : ssc1 = off b6[2] = 1 & b9[6] = 0 : ssc1 = on rw 0 5 clock frequency control bit4 latched input pcif_1 at power on rw x 4 clock frequency control bit3 latched input dot48 at power on rw x 3 clock frequency control bit2 latched input pcif_0 at power on rw x 2 clock frequency control bit1 latched input fs_a at power on rw x 1 clock frequency control bit0 latched input fs_b at power on rw x see table 6 0 frequency select mode bit 0 = freq. is selected by latched input fs_a and fs_b 1 = freq. is selected by i 2 c b9[5:1] rw 0
HD151TS207SS rev.1.00, apr.25.2 003, page 13 of 38 i 2 c controlled register bit map (cont.) table6 clock frequency function table fs_4 fs_3 fs_2 fs_a fs_b no. b9[5] b9[4] b9[3] b9[2] b9[1] cpu [mhz] src [mhz] 3v66 [mhz] pci [mhz] 0 0 0 0 0 0 100.02 100.02 66.68 33.34 1 0 0 0 0 1 200.03 100.02 66.68 33.34 2 0 0 0 1 0 133.36 100.02 66.68 33.34 3 0 0 0 1 1 166.69 100.02 66.68 33.34 4 0 0 1 0 0 200.03 100.02 66.68 33.34 5 0 0 1 0 1 400.07 100.02 66.68 33.34 6 0 0 1 1 0 266.71 100.02 66.68 33.34 7 0 0 1 1 1 333.39 100.02 66.68 33.34 8 0 1 0 0 0 138.69 100.02 66.68 33.34 9 0 1 0 0 1 142.25 100.02 66.68 33.34 10 0 1 0 1 0 145.80 100.02 66.68 33.34 11 0 1 0 1 1 149.36 100.02 66.68 33.34 12 0 1 1 0 0 152.91 100.02 66.68 33.34 13 0 1 1 0 1 156.47 100.02 66.68 33.34 14 0 1 1 1 0 160.03 100.02 66.68 33.34 15 0 1 1 1 1 163.58 100.02 66.68 33.34 16 1 0 0 0 0 167.14 100.02 66.68 33.34 17 1 0 0 0 1 170.70 100.02 66.68 33.34 18 1 0 0 1 0 174.25 100.02 66.68 33.34 19 1 0 0 1 1 177.81 100.02 66.68 33.34 20 1 0 1 0 0 181.36 100.02 66.68 33.34 21 1 0 1 0 1 184.92 100.02 66.68 33.34 22 1 0 1 1 0 186.70 100.02 66.68 33.34 23 1 0 1 1 1 189.36 100.02 66.68 33.34 24 1 1 0 0 0 192.03 100.02 66.68 33.34 25 1 1 0 0 1 194.70 100.02 66.68 33.34 26 1 1 0 1 0 197.37 100.02 66.68 33.34 27 1 1 0 1 1 200.03 100.02 66.68 33.34 28 1 1 1 0 0 202.70 100.02 66.68 33.34 29 1 1 1 0 1 205.37 100.02 66.68 33.34 30 1 1 1 1 0 208.03 100.02 66.68 33.34 31 1 1 1 1 1 210.70 100.02 66.68 33.34
HD151TS207SS rev.1.00, apr.25.2 003, page 14 of 38 i 2 c controlled register bit map (cont.) byte10 control register bit description contents type default note 7 rw 0 6 rw 0 5 ssc spread select bit[2:0] bit[2:0] = 000 = ?0.500%, 100 = 0.250% 001 = ?0.750%, 101 = 0.375% 010 = ?1.000%, 110 = 0.500% 011 = ?1.500%, 111 = 0.750% rw 0 4 backup of latch input fs_4 at power on rx 3 backup of latch input fs_3 at power on rx 2 backup of latch input fs_2 at power on rx 1 backup of latch input fs_a at power on rx 0 backup of latch input fs_b at power on when safe_f# is enable (b15[5]=1) pwrdwn#/safe_f# pin to ?low?, and if b23[1]=0, frequency selection is changed to these setting and pwrdwn#/safe_f# pin to ?high?, frequency selection is changed back to the last mode. rx byte11 control register bit description contents type default note 7 pci_stop# enable control bit 0 = enable , 1 = disable rw 0 6 cpu_stop# enable control bit 0 = enable , 1 = disable rw 0 5 pwrdwn# enable control bit 0 = enable , 1 = disable rw 0 4 backup of b9[5] written by i 2 crx 3 backup of b9[4] written by i 2 crx 2 backup of b9[3] written by i 2 crx 1 backup of b9[2] written by i 2 crx 0 backup of b9[1] written by i 2 c when safe_f# is enable (b15[5]=1) pwrdwn#/safe_f# pin to ?low?, and if b23[1]=1, frequency selection is changed to these setting and pwrdwn#/safe_f# pin to ?high?, frequency selection is changed back to the last mode. rx
HD151TS207SS rev.1.00, apr.25.2 003, page 15 of 38 i 2 c controlled register bit map (cont.) byte12 control register bit description contents type default note 7 reserved r/w 0 6 reserved r/w 0 5 reserved r/w 0 4 reserved r/w 0 3 reserved r/w 0 2 pll1 output (vco1) frequency control bit (m1/n1 divider control bit) pll1 : for src/3v66/pci_pll 0 = normal mode pll1 m1[6:0] and n1[9:0] are changed on table 5 selection decided by fs4/3/2/a/b or b9[5:1] 1 = over or down clocking mode pll1 m1[6:0] and n1[9:0] are changed by b12[1:0], b13[7:0] and b14[6:0]. b12[1:0], b13[7: 0] and b14[6:0] are able to be changed at b12[2] = 1. r/w 0 1 pll1 n1 divider control bit9 n1[9] r/w 0 0 pll1 n1 divider control bit8 n1[8] r/w 0 see. note 1 note: 1. b12[1:0], b13[7:0] and b14[ 6:0] must be written together (a t writing b14) in every case. byte13 control register bit description contents type default note 7 pll1 n1 divider control bit7 n1[7] r/w 0 6 pll1 n1 divider control bit6 n1[6] r/w 1 5 pll1 n1 divider control bit5 n1[5] r/w 0 4 pll1 n1 divider control bit4 n1[4] r/w 0 3 pll1 n1 divider control bit3 n1[3] r/w 1 2 pll1 n1 divider control bit2 n1[2] r/w 0 1 pll1 n1 divider control bit1 n1[1] r/w 1 0 pll1 n1 divider control bit0 n1[0] r/w 1 see note 1 note: 1. b12[1:0], b13[7:0] and b14[ 6:0] must be written together (a t writing b14) in every case.
HD151TS207SS rev.1.00, apr.25.2 003, page 16 of 38 i 2 c controlled register bit map (cont.) byte14 control register bit description contents type default note 7 reserved r/w 0 6 pll1 m1 divider control bit6 m1[6] r/w 0 5 pll1 m1 divider control bit5 m1[5] r/w 0 4 pll1 m1 divider control bit4 m1[4] r/w 1 3 pll1 m1 divider control bit3 m1[3] r/w 0 2 pll1 m1 divider control bit2 m1[2] r/w 0 1 pll1 m1 divider control bit1 m1[1] r/w 1 0 pll1 m1 divider control bit0 m1[0] r/w 0 see note 1 note: 1. b12[1:0], b13[7:0] and b14[ 6:0] must be written together (a t writing b14) in every case. byte15 control register bit description contents type default note 7 pci_5 output frequency select bit 0 = 33.3 mhz, 1 = 25 mhz r/w 0 6 usb_48 output frequency select bit 0 = 48mhz, 1 = 24 mhz r/w 0 5 safe_f# input mode select bit 0 = pwrdwn# input mode 1 = safe_f# input mode default is pwrdwn# input. safe_f# is active ?low? input. when safe_f# is ?low?, frequency mode is changed to the predefined frequency mode. predefined frequency mode is selected by b23[1]. r/w 0 4 clock divider control bit 0 = normal mode clock dividers are changed by table 5 selection decided b9[5:1] 1 = over or down clocking mode clock dividers are changed by b15[3:0] and b16[7:0]. b15[3:0] and b16[ 7:0] are able to be changed at b15[4] = 1. r/w 0 3 cpu divider control bit3 r/w x 2 cpu divider control bit2 r/w x 1 cpu divider control bit1 r/w x 0 cpu divider control bit0 0001 = 1/1, 0010 = 1/2, 0011 = 1/3, 0100 = 1/4, 0101 = 1/5, 0110 = 1/6, 0111 = 1/7 1000 = 1/8 1001 = 1/9 1010 = 1/10 1011 = 1/11 r/w x
HD151TS207SS rev.1.00, apr.25.2 003, page 17 of 38 i 2 c controlled register bit map (cont.) byte16 control register bit description contents type default note 3v66 divider ratio = 7 3v66 / pci / pcif divider control bit3 r/w x 6 3v66 / pci / pcif divider control bit2 0010 = 1/2, 0011 = 1/3, 0100 = 1/4, 0101 = 1/5, 0110 = 1/6, 0111 = 1/7 1000 = 1/8 1001 = 1/9 1010 = 1/10 1011 = 1/11 r/w x 5 3v66 / pci / pcif divider control bit1 r/w x 4 3v66 / pci / pcif divider control bit0 pci / pcif divider ratio = 3v66 x 1/2 r/w x 3 src divider control bit3 r/w x 2 src divider control bit2 r/w x 1 src divider control bit1 r/w x 0 src divider control bit0 0001 = 1/1, 0010 = 1/2, 0011 = 1/3, 0100 = 1/4, 0101 = 1/5, 0110 = 1/6 0111 = 1/7 1000 = 1/8 1001 = 1/9 1010 = 1/10 1011 = 1/11 r/w x byte17 control register bit description contents type default note 7 reserved r/w 0 6 reserved r/w 0 5 reserved r/w 0 4 pll2 output (vco2) frequency control bit (m2 / n2 divider control bit) pll2 : for cpu 0 = normal mode vco2 frequency is changed on table 5 selection decided by fs4/3/2/a/b or b9[5:1]. 1 = over or down clocking mode vco2 frequency is changed by b17[3:0] and b18[7:0] with decimal. b17[3:0] and b18[ 7:0] are able to be changed at b17[4] = 1. r/w 0 3 vco2 frequency control bit11 r/w 0 2 vco2 frequency control bit10 r/w 1 1 vco2 frequency control bit9 r/w 0 0 vco2 frequency control bit8 these bits are 100mhz digit of vco2 frequency. 0000 = 0, 0001 = 1 ?. 1001 = 9 r/w 0 see note 1 note: 1. b17[3:0] and b18[7:0] must be written together (at writing b18) in every case.
HD151TS207SS rev.1.00, apr.25.2 003, page 18 of 38 i 2 c controlled register bit map (cont.) byte18 control register bit description contents type default note 7 vco2 frequency control bit7 r/w 0 6 vco2 frequency control bit6 r/w 0 5 vco2 frequency control bit5 r/w 0 4 vco2 frequency control bit4 these bits are 10mhz digit of vco2 frequency. 0000 = 0, 0001 = 1 ?. 1001 = 9 r/w 0 3 vco2 frequency control bit3 r/w 0 2 vco2 frequency control bit2 r/w 0 1 vco2 frequency control bit1 r/w 0 0 vco2 frequency control bit0 these bits are 1mhz digit of vco2 frequency. 0000 = 0, 0001 = 1 ?. 1001 = 9 r/w 0 see note 1 note: 1. b17[3:0] and b18[7:0] must be written together (at writing b18) in every case. how to set vco2 frequency to 666 mhz. 0001011 0 on write byte17 6 01100110 byte18 6 6 max 720 min 200 how to read actual frequency of vco2 and cpu clock 01101000 byte20 8 6 01100110 byte17[4] = 1 actual vco2 freq. read back. byte19 6 6 note: case of vco2 = 666.8 mhz. other clock frequency are able to read using the same way as shown at upper. byte19, byte20 = read back of vco2 actual frequency. byte21, byte22 = read back of cpu actual frequency.
HD151TS207SS rev.1.00, apr.25.2 003, page 19 of 38 i 2 c controlled register bit map (cont.) byte19 control register bit description contents type default note 7 vco2 frequency read bit15 r 0 6 vco2 frequency read bit14 r 0 5 vco2 frequency read bit13 r 0 4 vco2 frequency read bit12 calculation result of vco2 frequency. 100 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 3 vco2 frequency read bit11 r 0 2 vco2 frequency read bit10 r 0 1 vco2 frequency read bit9 r 0 0 vco2 frequency read bit8 calculation result of vco2 frequency. 10 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 byte20 control register bit description contents type default note 7 vco2 frequency read bit7 r 0 6 vco2 frequency read bit6 r 0 5 vco2 frequency read bit5 r 0 4 vco2 frequency read bit4 calculation result of vco2 frequency. 1 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 3 vco2 frequency read bit3 r 0 2 vco2 frequency read bit2 r 0 1 vco2 frequency read bit1 r 0 0 vco2 frequency read bit0 calculation result of vco2 frequency. 0.1 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 byte21 control register bit description contents type default note 7 cpu frequency read bit15 r 0 6 cpu frequency read bit14 r 0 5 cpu frequency read bit13 r 0 4 cpu frequency read bit12 calculation result of cpu frequency. 100 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 3 cpu frequency read bit11 r 0 2 cpu frequency read bit10 r 0 1 cpu frequency read bit9 r 0 0 cpu frequency read bit8 calculation result of cpu frequency. 10 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0
HD151TS207SS rev.1.00, apr.25.2 003, page 20 of 38 i 2 c controlled register bit map (cont.) byte22 control register bit description contents type default note 7 cpu frequency read bit7 r 0 6 cpu frequency read bit6 r 0 5 cpu frequency read bit5 r 0 4 cpu frequency read bit4 calculation result of cpu frequency. 1 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 3 cpu frequency read bit3 r 0 2 cpu frequency read bit2 r 0 1 cpu frequency read bit1 r 0 0 cpu frequency read bit0 calculation result of cpu frequency. 0.1 mhz digit 0000 = 0, 0001 = 1 ?. 1001 = 9 r0 byte23 control register bit description contents type default note 7 watchdog enable control bit 0 = disable , pin22 = 3v66_0 output 1 = enable , pin22 = reset# output r/w 0 6 reset# reverse control bit 0 = normal , 1 = reverse r/w 0 5 watchdog timer count bit3 r/w 1 4 watchdog timer count bit2 r/w 0 3 watchdog timer count bit1 r/w 0 2 watchdog timer count bit0 these 4 bits corresponds to how many watchdog timer will wait from becoming ?alarm mode? (b23[0] = 1) to outputting reset# pin to ?low?. default is 586ms x8 = 4.7s at power on r/w 0 1 backup frequency select bit 0 = b10[4:0] , 1 = b11[4:0] when safe_f# is ?low? , frequency mode is changed to the predefined frequency mode decided by b10[4:0] or b11[4:0]. r/w 0 0 watchdog status bit 0 = normal mode, 1 = alarm mode r/w 0
HD151TS207SS rev.1.00, apr.25.2 003, page 21 of 38 i 2 c controlled register bit map (cont.) byte24 control register bit description contents type default note 7 reserved r/w 0 6 pci_stop# stop pci_6 control bit 0 = stoppable, 1 = free running r/w 0 5 pci_stop# stop pci_5 control bit 0 = stoppable, 1 = free running r/w 0 4 pci_stop# stop pci_4 control bit 0 = stoppable, 1 = free running r/w 0 3 pci_stop# stop pci_3 control bit 0 = stoppable, 1 = free running r/w 0 2 pci_stop# stop pci_2 control bit 0 = stoppable, 1 = free running r/w 0 1 pci_stop# stop pci_1 control bit 0 = stoppable, 1 = free running r/w 0 0 pci_stop# stop pci_0 control bit 0 = stoppable, 1 = free running r/w 0 byte25 control register bit description contents type default note 7 cpu clock skew1 control bit3 r/w 1 6 cpu clock skew1 control bit2 r/w 0 5 cpu clock skew1 control bit1 r/w 0 4 cpu clock skew1 control bit0 delay ahead 1000 = +0.00ns, 0111 = ?0.20ns 1001 = +0.20ns, 0110 = ?0.40ns 1010 = +0.40ns, 0101 = ?0.60ns 1011 = +0.60ns, 0100 = ?0.80ns 1100 = +0.80ns, 0011 = ?1.00ns 1101 = +1.00ns, 0010 = ?1.20ns 1110 = +1.20ns, 0001 = ?1.40ns 1111 = +1.40ns, 0000 = ?1.60ns r/w 0 see note 1 3 cpu clock skew2 control bit3 r/w 1 2 cpu clock skew2 control bit2 r/w 0 1 cpu clock skew2 control bit1 r/w 0 0 cpu clock skew2 control bit0 delay ahead 1000 = +0.00ns, 0111 = ?0.15ns 1001 = +0.15ns, 0110 = ?0.30ns 1010 = +0.30ns, 0101 = ?0.45ns 1011 = +0.45ns, 0100 = ?0.60ns 1100 = +0.60ns, 0011 = ?0.75ns 1101 = +0.75ns, 0010 = ?0.90ns 1110 = +0.90ns, 0001 = ?1.05ns 1111 = +1.05ns, 0000 = ?1.20ns r/w 0 see note 1 note: 1. total cpu clock skew is skew1+skew2.
HD151TS207SS rev.1.00, apr.25.2 003, page 22 of 38 i 2 c controlled register bit map (cont.) byte26 control register bit description contents type default note 7 pcif / pci clock skew2 control bit3 r/w 0 6 pcif / pci clock skew2 control bit2 r/w 0 5 pcif / pci clock skew2 control bit1 r/w 0 4 pcif / pci clock skew2 control bit0 skew2 is ?late? skew that is delay time from ?normal? skew1. 0000 = +0.0ns, 1000 = +3.2ns 0001 = +0.4ns, 1001 = +3.6ns 0010 = +0.8ns, 1010 = +4.0ns 0011 = +1.2ns, 1011 = +4.4ns 0100 = +1.6ns, 1100 = +4.8ns 0101 = +2.0ns, 1101 = +5.2ns 0110 = +2.4ns, 1110 = +5.6ns 0111 = +2.8ns, 1111 = +6.0ns r/w 0 see note 1 3 pcif / pci clock skew1 control bit3 r/w 1 2 pcif / pci clock skew1 control bit2 r/w 0 1 pcif / pci clock skew1 control bit1 r/w 0 0 pcif / pci clock skew1 control bit0 skew1 is ?normal? skew. delay ahead 1000 = +0.0ns, 0111 = ?0.4ns 1001 = +0.4ns, 0110 = ?0.8ns 1010 = +0.8ns, 0101 = ?1.2ns 1011 = +1.2ns, 0100 = ?1.6ns 1100 = +1.6ns, 0011 = ?2.0ns 1101 = +2.0ns, 0010 = ?2.4ns 1110 = +2.4ns, 0001 = ?2.8ns 1111 = +2.8ns, 0000 = ?3.2ns r/w 0 see note 1 note: 1. pcif / pci clock skew is skew1 (= normal) or skew1+skew2 (= late). byte27 control register bit description contents type default note 7 reserved r/w 0 6 pcif_2 skew select bit 0 = normal, 1 = late r/w 0 5 pcif_1 skew select bit 0 = normal, 1 = late r/w 0 4 pcif_0 skew select bit 0 = normal, 1 = late r/w 0 see note 1 3 3v66 clock skew control bit3 r/w 1 2 3v66 clock skew control bit2 r/w 0 1 3v66 clock skew control bit1 r/w 0 0 3v66 clock skew control bit0 delay ahead 1000 = +0.0ns, 0111 = ?0.4ns 1001 = +0.4ns, 0110 = ?0.8ns 1010 = +0.8ns, 0101 = ?1.2ns 1011 = +1.2ns, 0100 = ?1.6ns 1100 = +1.6ns, 0011 = ?2.0ns 1101 = +2.0ns, 0010 = ?2.4ns 1110 = +2.4ns, 0001 = ?2.8ns 1111 = +2.8ns, 0000 = ?3.2ns r/w 0 note: 1. normal = skew1(b26[3:0]), late = skew1(b26[3:0]) +skew2 (b26[7:4]).
HD151TS207SS rev.1.00, apr.25.2 003, page 23 of 38 i 2 c controlled register bit map (cont.) byte28 control register bit description contents type default note 7 reserved 0 = normal, 1 = late r/w 0 6 pci_6 skew select bit 0 = normal, 1 = late r/w 0 5 pci_5 skew select bit 0 = normal, 1 = late r/w 0 4 pci_4 skew select bit 0 = normal, 1 = late r/w 0 3 pci_3 skew select bit 0 = normal, 1 = late r/w 0 2 pci_2 skew select bit 0 = normal, 1 = late r/w 0 1 pci_1 skew select bit 0 = normal, 1 = late r/w 0 0 pci_0 skew select bit 0 = normal, 1 = late r/w 0 see note 1 note: 1. normal = skew1(b26[3:0]), late = skew1(b26[3:0]) +skew2 (b26[7:4]). byte29 control register bit description contents type default note 7 vch slew rate control bit1 r/w 1 6 vch slew rate control bit0 00 = normal, 10 = ?++? 01 = ?+? , 11 = ??? r/w 0 5 pci slew rate control bit1 r/w 1 4 pci slew rate control bit0 00 = normal, 10 = ?++? 01 = ?+? , 11 = ??? r/w 0 3 pcif slew rate control bit1 r/w 1 2 pcif slew rate control bit0 00 = normal, 10 = ?++? 01 = ?+? , 11 = ??? r/w 0 1 3v66 slew rate control bit1 r/w 1 0 3v66 slew rate control bit0 00 = normal, 10 = ?++? 01 = ?+? , 11 = ??? r/w 0
HD151TS207SS rev.1.00, apr.25.2 003, page 24 of 38 clock stop timing diagram 6 2 tristate (controled by byte2[6]) tristate pci_stop# pci_f pci src (stoppable) pci_stop# assertion/de-assersion pci_stop# assertion/de-assertion waveforms low pwrdwn# cpu (stoppable) cpu# (stoppable) cpu (stoppable) pwrdwn# assertion/de-assersion pwrdwn# assertion/de-assertion waveforms 6 6 < 1.8 ms pwrdwn# pwrdwn# functionality cpu# cpu src src# 3v66 66mhz normal normal normal float float low pcif/pci 33mhz low usb/dot 48mhz low ref 14.318mhz low src (stoppable) src# (stoppable) float (controled by byte2[5:3]) float 1 normal iref:2 or float iref:2 or float 0
HD151TS207SS rev.1.00, apr.25.2 003, page 25 of 38 renesas clock generator i 2 c serial interface operation 1. write mode 1.1 controller (host) sends a start bit. 1.2 controller (host) sends the write address d2 (h). 1.3 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 1.4 controller (host) sends a begin byte m. 1.5 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 1.6 controller (host) sends a byte count n. 1.7 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 1.8 controller (host) sends data from byte m to byte m+n?1. 1.9 renesas clock generator will acknowledge each byte one at a time. 1.10 controller (host) sends a stop bit. start bit 1 bit 1 bit 1 bit 1 bit 1 bit 7 bits 8 bits 8 bits 8 bits byte m slave address begin byte = m byte count = n r/w d2(h) ack 1 bit ack 1 bit ack ack ack byte m+1 8 bits 1 bit 1 bit stop bit 8 bits byte m+n?1 ack
HD151TS207SS rev.1.00, apr.25.2 003, page 26 of 38 renesas clock generator i 2 c serial interface operation (cont.) 2. read mode 2.1 controller (host) sends a start bit. 2.2 controller (host) sends the write address d2 (h). 2.3 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 2.4 controller (host) sends a begin byte m. 2.5 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 2.6 controller (host) sends a restart bit. 2.7 controller (host) sends the read address d3 (h). 2.8 renesas clock generator will acknowledge (renesas clock gen. sends ?low?). 2.9 renesas clock generator will send the byte count n. 2.10 controller (host) will acknowledge. 2.11 renesas clock generator will send data from byte m to byte m+n?1. 2.12 when renesas clock generator sends the last byte, controller (host) will not acknowledge. 2.13 controller (host) sends a stop bit. start bit 1 bit 1 bit 1 bit 1 bit 1 bit 7 bits 8 bits 7 bits 1 bit restart bit slave address slave address r/w d2(h) r/w d3(h) ack 1 bit ack 1 bit ack 1 bit ack 1 bit ack ack begin count = n 8 bits 1 bit 1 bit stop bit 8 bits byte m+n?1 8 bits 8 bits byte m byte m+1 not ack begin byte = m notes: 1. renesas clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for the verification. 2. the data transfer rate supported by this cl ock generator is 100k bits/sec or less (standard mode). 3. the input is operating at 3.3 v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is se t to use only block-write from the controller. 6. the bytes must be accessed in sequential order fr om lowest to highest byte with the ability to stop after any complete byte has been transferre d. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown.
HD151TS207SS rev.1.00, apr.25.2 003, page 27 of 38 absolute maximum ratings item symbol ratings unit conditions supply voltage vdd ?0.5 to 4.6 v input voltage v i ?0.5 to 4.6 v output voltage *1 v o ?0.5 to vdd +0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to vdd maximum power dissipation at ta = 55c (in still air) 0.7 w storage temperature tstg ?65 to +150 c notes: stresses beyond those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ratings only, an d functional operation of the device at these or any other conditions beyond those indicated un der ?recommended operating conditions? is not implied. exposure to absolute maximum rated co nditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions item symbol min typ max unit conditions supply voltage vdd 3.135 3.3 3.465 v supply voltage vdda 3.135 3.3 3.465 v dc input signal voltage ?0.3 ? vdd+0.3 v high level input voltage v ih 2.0 ? vdd+0.3 v low level input voltage v il ?0.3 ? 0.8 v operating temperature t a 0?70c
HD151TS207SS rev.1.00, apr.25.2 003, page 28 of 38 dc electrical characterist ics / serial input port ta = 0c to 70c, vdd = 3.3 v item symbol min typ * 1 max unit test conditions input low voltage v il ?? 0.8 v input high voltage v ih 2.0 ?? v input current i i ?50 ? +50 a vi = 0 v or 3.465 v, vdd = 3.465 v input capacitance c i ? 10 ? pf sdata & sclk note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characterist ics / serial input port ta = 0c to 70c, vdd = 3.3 v item symbol min typ max unit test conditions notes sclk frequency f sclk ?? 100 khz normal mode start hold time t sthd 4.0 ?? s sclk low time t low 4.7 ?? s sclk high time t high 4.0 ?? s data setup time t dsu 250 ?? ns data hold time t dhd 300 ?? ns stop setup time t stsu 4.0 ?? s bus free time between stop & start condition t spf 4.7 ?? s
HD151TS207SS rev.1.00, apr.25.2 003, page 29 of 38 dc electrical characteristics cpu/cpu# clock ta = 0c to 70c, vdd = 3.3 v, iref = 475 ? item symbol min typ * 1 max unit test conditions output voltage v o ?? 1.20 v rp = 49.9 ? , vdd = 3.3 v output current i o ? i(nom) * 2 ? ma vdd = 3.3 v output resistance 3000 ??? v o = 1.2 v notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditionai (nom) is out put current(ioh) shown in below. 2. ioh = vdd/(3rr) = 3. 3/(3x475) = 2.32 ma, ioh x6 = 13.89 ma (voh @z: 0.695 v @50 ? ), ioh x2 = 4.63 ma (voh @z: 0.232 v @50 ? ) ac electrical characteristics cpu/cp u# clock (cpu at 0.7v timing) ta = 0c to 70c, vdd = 3.3 v, c l = 2 pf, rs = 33.2 ? ? item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |125| ? ps note1 cpu group skew (cpu clock out to cpu clock out) t sks ? |100| ? ps rise time t r 175 ? 700 ps v o = 0.175 v to 0.525 v 200mhz fall time t f 175 ? 700 ps v o = 0.175 v to 0.525 v 200mhz clock duty cycle 45 50 55 % 200mhz cpu clock period(100) ? 9.99 ? ns cpu clock period(133) ? 7.49 ? ns cpu clock period(166) ? 5.99 ? ns cpu clock period(200) ? 4.99 ? ns cross point(0.7v) voltage vcross 0.25 ? 0.55 v 200mhz note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 30 of 38 dc electrical characteristics src/src# clock ta = 0c to 70c, vdd = 3.3 v, iref = 475 ? item symbol min typ *1 max unit test conditions output voltage v o ?? 1.20 v rp = 49.9 ? , vdd = 3.3 v output current i o ? i(nom) ? ma vdd = 3.3 v output resistance 3000 ??? v o = 1.2 v notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions 2. i(nom) is output current(ioh) shown in below. ioh = vdd/(3rr) = 3. 3/(3x475) = 2.32 ma, ioh x6 = 13.89 ma (voh @z: 0.695v @50 ? ), ioh x2 = 4.63 ma (voh @z: 0.232v @50 ? ) ac electrical characteristics src/ src# clock (src at 0.7v timing) ta = 0c to 70c, vdd = 3.3 v, c l = 2 pf, rs = 33.2 ? ? item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |125| ? ps note1 rise time t r 175 ? 700 ps v o = 0.175 v to 0.525 v 100 mhz fall time t f 175 ? 700 ps v o = 0.175 v to 0.525 v 100 mhz clock duty cycle 45 50 55 % 100 mhz src clock period(100) ? 9.99 ? ns src clock period(200) ? 4.99 ? ns cross point(0.7v) voltage vcross 0.25 ? 0.55 v 100 mhz note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 31 of 38 dc electrical characteristics / 3v66 buffer (ck409t type5 buffer) ta = 0c to 70c, vdd = 3.3 v item symbol min typ *1 max unit test conditions v oh 3.1 ?? vi oh = ?1 ma, vdd = 3.3 v output voltage v ol ?? 50 mv i ol = 1 ma, vdd = 3.3 v i oh ?? ?33 ma v oh = 1.0 v output current i ol 30 ?? ma v ol = 1.95 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characteristics / 3v66 buffer ta = 0c to 70c, vdd = 3.3 v, c l = 30 pf item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |250| ? ps fig.1 note1 3v66 buffer (3v66 (4:0)) group skew t sks ? 0 250 ps rising edge @1.5 v to 1.5 v fig.2 slew rate t sl 1.0 ? 4.0 v/ns 0.4v to 2.4 v clock period ? 14.998 ? ns clock duty cycle 455055% 3v66 (4:0) leads 33 mhz pci 1.5 ? 3.5 ns note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 32 of 38 dc electrical characteristics / pci & pcif clock (ck409t type5 buffer) ta = 0c to 70c, vdd = 3.3 v item symbol min typ * 1 max unit test conditions v oh 3.1 ?? vi oh = ?1 ma, vdd = 3.3 v output voltage v ol ?? 50 mv i ol = 1 ma, vdd = 3.3 v i oh ?? ?33 ma v oh = 1.0 v output current i ol 30 ?? ma v ol = 1.95 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characteristics / pci & pcif clock ta = 0c to 70c, vdd = 3.3 v, c l = 30 pf item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |250| ? ps fig.1 note1 pci group skew tsks ? 0 500 ps rising edge @1.5v to 1.5 v fig.2 clock period ? 29.996 ? ns slew rate t sl 1.0 ? 4.0 v/ns 0.4 v to 2.4 v clock duty cycle 455055% note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 33 of 38 dc electrical characteristics / usb & vch 48mhz clock (ck409t type3a buffer) ta = 0c to 70c, vdd = 3.3 v item symbol min typ * 1 max unit test conditions v oh 3.1 ?? vi oh = ?1 ma, vdd = 3.3 v output voltage v ol ?? 50 mv i ol = 1 ma, vdd = 3.3 v i oh ?? ?29 ma v oh = 1.0 v output current i ol 29 ?? ma v ol = 1.95 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characteristics / usb & vch 48mhz clock ta = 0c to 70c, vdd = 3.3 v, c l = 20 pf item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |350| ? ps fig.1 note1 clock period ? 20.831 ? ns slew rate t sl 1.0 ? 2.0 v/ns 0.4 v to 2.4 v clock duty cycle 455055% note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 34 of 38 dc electrical characteristics / do t clock (ck409t type3b buffer) ta = 0c to 70c, vdd = 3.3 v item symbol min typ *1 max unit test conditions v oh 3.1 ?? vi oh = ?1 ma, vdd = 3.3 v output voltage v ol ?? 50 mv i ol = 1 ma, vdd = 3.3 v i oh ?? ?29 ma v oh = 1.0 v output current i ol 29 ?? ma v ol = 1.95 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characteristics / dot clock ta = 0c to 70c, vdd = 3.3 v, c l = 10 pf item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |350| ? ps fig.1 note1 clock period ? 20.831 ? ns slew rate t sl 2.0 ? 4.0 v/ns 0.4v to 2.4v clock duty cycle 455055% note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 35 of 38 dc electrical characteristics / ref clock (ck409t type5 buffer) ta = 0c to 70c, vdd = 3.3 v item symbol min typ *1 max unit test conditions v oh 3.1 ?? vi oh = ?1 ma, vdd = 3.3 v output voltage v ol ?? 50 mv i ol = 1 ma, vdd = 3.3 v i oh ?? ?33 ma v oh = 1.0 v output current i ol 30 ?? ma v ol = 1.95 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ac electrical characteristics / ref clock ta = 0c to 70c, vdd = 3.3 v, c l = 30 pf item symbol min typ max unit test conditions notes cycle to cycle jitter t ccs ? |1000| ? ps fig.1 note1 clock period ? 69.841 ? ns slew rate t sl 1.0 ? 4.0 v/ns 0.4 v to 2.4 v clock duty cycle 455055% note: 1. difference of cycle time between two adjoining cycles.
HD151TS207SS rev.1.00, apr.25.2 003, page 36 of 38 clock out tcycle n t = (tcycle n) - (tcycle n+1) ccs tcycle n+1 fig.1 cycle to cycle jitter (3.3 v single ended clock output) clock outx clock outy 1.5 v tsks 1.5 v fig.2 output clock skew (3.3v single ended clock output) r p = 49.9 ? r p = 49.9 ? z lt = z lc = 50 ? r s = 33.2 ? cpu lt cpu# ts207 c l = 2 pf c l = 2 pf r s = 33.2 ? lc r i(ref) = 475 ? fig.3 load circuit for cpu/cpu#
HD151TS207SS rev.1.00, apr.25.2 003, page 37 of 38 package dimensions unit : mm 0.10(0.004) 7.50 128 29 56 18.40 0.25 0.635 0.3 2.6 10.35 0.76 0.5 0?? 8? 0.2
HD151TS207SS rev.1.00, apr.25.2 003, page 38 of 38 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0

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